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general description the ds4520 is a 9-bit nonvolatile (nv) i/o expander with 64 bytes of nv user memory controlled by an i 2 c tm - compatible serial interface. the ds4520 offers users a digitally programmable alternative to hardware jumpers and mechanical switches that are being used to control digital logic nodes. furthermore, the digital state of each pin can be read through the serial interface. each i/o pin is independently configurable. the outputs are open drain with selectable pullups. each output has the ability to sink up to 12ma. since the device is nv, it powers up in the desired state allowing it to control digital logic inputs immediately on power-up without having to wait for the host cpu to initiate control. applications ram-based fpga bank switching for multiple profiles selecting between boot flash setting asic configurations/profiles servers network storage routers telecom equipment pc peripherals features ? programmable replacement for mechanical jumpers and switches ? nine nv input/output pins ? 64-byte nv user memory (eeprom) ? i 2 c-compatible serial interface ? up to 8 devices can be multidropped on the same i 2 c bus ? open-drain outputs with configurable pullups ? outputs capable of sinking 12ma ? low power consumption ? wide operating voltage (2.7v to 5.5v) ? operating temperature range: -40c to +85c ds4520 9-bit i 2 c nonvolatile i/o expander plus memory ______________________________________________ maxim integrated products 1 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 i/o_0 gnd i/o_8 i/o_7 i/o_6 i/o_5 a2 scl sda top view i/o_1 i/o_2 a0 i/o_3 i/o_4 a1 v cc ds4520 pin configuration scl i/o_0 i/o_1 i/o_2 i/o_3 i/o_4 i/o_5 i/o_6 i/o_7 i/o_8 sda a0 a1 a2 gnd from system controller fpga clock generator cpu speed select 4.7k ? 4.7k ? 0.1 f v cc v cc ds4520 t ypical operating circuit rev 0; 6/04 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. add ?t&r?for tape and reel orders. ordering information i 2 c is a trademark of philips corp. purchase of i 2 c components from maxim integrated products, inc., or one of its sublicensed associated companies, conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. part temp range pin-package ds4520e -40? to +85? 16 tssop
ds4520 9-bit i 2 c nonvolatile i/o expander plus memory 2 _____________________________________________________________________ absolute maximum ratings recommended dc operating conditions (t a = -40? to +85?) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage on v cc , sda, and scl pins relative to ground.............................................-0.5v to +6.0v voltage on a0, a1, a2, and i/o_n [n = 0 to 8] relative to ground....-0.5v to (v cc + 0.5v) not to exceed +6.0v operating temperature range ...........................-40? to +85? eeprom programming temperature range .........0? to +70? storage temperature range .............................-55? to +125? soldering temperature ...see ipc/jedec j-std-020a specification parameter symbol conditions min typ max units supply voltage v cc (note 1) +2.7 +5.5 v input logic 1 v ih 0.7 x v cc v cc + 0.3 v input logic 0 v il -0.3 0.3 x v cc v dc electrical characteristics (v cc = +2.7v to +5.5v; t a = -40? to +85?, unless otherwise noted.) parameter symbol conditions min typ max units standby current i stby (note 2) 2 10 a input leakage i l -1.0 +1.0 a input current each i/o pin i i/o 0.4v < v i/o < 0.9v cc (note 3) -1.0 +1.0 a 3ma sink current 0 0.4 low-level output voltage (sda) v ol sda 6ma sink current 0 0.6 v i/o pin low-level output voltage v ol i/o 12ma sink current 0.4 v i/o pin pullup resistors r pu 4.0 5.5 7.5 k ? i/o capacitance c i/o (note 4) 10 pf power-on reset voltage v por 1.6 v
ds4520 9-bit i 2 c nonvolatile i/o expander plus memory _____________________________________________________________________ 3 note 1: all voltages referenced to ground. note 2: i stby is specified with sda = scl = v cc , outputs floating, and inputs connected to v cc or gnd. note 3: the ds4520 does not obstruct the sda and scl lines if v cc is switched off as long as the voltages applied to these inputs do not violate their minimum and maximum input voltage levels. note 4: guaranteed by design. note 5: timing shown is for fast-mode (400khz) operation. this device is also backward compatible with i 2 c standard-mode timing. note 6: c b ?otal capacitance of one bus line in picofarads. note 7: eeprom write time applies to all the eeprom memory and sram shadowed eeprom memory when see = 0. the eeprom write time begins after a stop condition occurs. ac electrical characteristics (see figure 2) (v cc = +2.7v to +5.5v; t a = -40? to +85?, unless otherwise noted. timing referenced to v il(max) and v ih(min) .) parameter symbol conditions min typ max units scl clock frequency f scl (note 5) 0 400 khz bus free time between stop and start conditions t buf 1.3 ? hold time (repeated) start condition t hd:sta 0.6 ? low period of scl t low 1.3 ? high period of scl t high 0.6 ? data hold time t hd:dat 0 0.9 ? data setup time t su:dat 100 ns start setup time t su:sta 0.6 ? sda and scl rise time t r (note 6) 20 + 0.1c b 300 ns sda and scl fall time t f (note 6) 20 + 0.1c b 300 ns stop setup time t su:sto 0.6 ? sda and scl capacitive loading c b (note 6) 400 pf eeprom write time t wr (note 7) 10 20 ms nonvolatile memory characteristics (v cc = +2.7v to +5.5v, unless otherwise noted.) parameter symbol conditions min typ max units eeprom writes +70? (note 4) 50,000
ds4520 9-bit i 2 c nonvolatile i/o expander plus memory 4 _____________________________________________________________________ t ypical operating characteristics (v cc = +5.0v, t a = +25?, unless otherwise noted.) supply current vs. supply voltage ds4520 toc01 supply voltage (v) supply current ( a) 4.5 4.0 3.5 0.5 1.0 1.5 2.0 0 3.0 5.0 i/o0?/o7 control bits = 0 i/o0?/o7 pullups disabled v cc = sda = scl supply current vs. temperature ds4520 toc02 temperature ( c) supply current ( a) 80 60 40 20 0 -20 0.5 1.0 1.5 2.0 2.5 0 -40 i/o0?/o7 control bits = 0 i/o0?/o7 pullups disabled v cc = sda = scl = 5v supply current vs. scl frequency ds4520 toc03 scl frequency (khz) supply current ( a) 300 200 100 2 4 6 8 10 12 14 16 18 20 0 0400 v cc = sda = 5v i/o output voltage vs. supply voltage ds4520 toc04 supply voltage (v) i/o voltage (v) 5 4 3 2 1 1 2 3 4 5 6 0 06 pullups enabled pulldowns disabled high impedance eeprom recall at v por
ds4520 9-bit i 2 c nonvolatile i/o expander plus memory _____________________________________________________________________ 5 pin description pin name function 1 i/o_0 input/output 0. bidirectional i/o pin. 2 i/o_1 input/output 1. bidirectional i/o pin. 3 i/o_2 input/output 2. bidirectional i/o pin. 4 i/o_3 input/output 3. bidirectional i/o pin. 5 i/o_4 input/output 4. bidirectional i/o pin. 6a0i 2 c address input. inputs a0, a1, and a2 determine the i 2 c slave address of the device. 7a1i 2 c address input. inputs a0, a1, and a2 determine the i 2 c slave address of the device. 8v cc power-supply voltage 9 sda i 2 c serial data open-drain input/output 10 scl i 2 c serial clock input 11 a2 i 2 c address input. inputs a0, a1, and a2 determine the i 2 c slave address of the device. 12 i/o_5 input/output 5. bidirectional i/o pin. 13 i/o_6 input/output 6. bidirectional i/o pin. 14 i/o_7 input/output 7. bidirectional i/o pin. 15 i/o_8 input/output 8. bidirectional i/o pin. 16 gnd ground ds4520 i/o control registers i/o cell (x9) i/o_n [n = 0 to 8] r pu pullup enable (f0h-f1h) i/o control (f2h-f3h) i/o status (f8h-f9h) i 2 c interface sda scl a0 a1 a2 gnd eeprom 64 bytes user memory [00h to 3fh] v cc v cc v cc block diagram
ds4520 9-bit i 2 c nonvolatile i/o expander plus memory 6 _____________________________________________________________________ detailed description the ds4520 contains nine bidirectional, nv, input/out- put (i/o) pins, and a 64-byte eeprom user memory. the i/o pins and user memory are accessible through an i 2 c-compatible serial bus. programmable nv i/o pins each programmable i/o pin consists of an input and an open-collector output with a selectable internal pullup resistor. to enable the pullups for each i/o pin, write to the pullup enable registers (f0h and f1h). to pull the output low or place the pulldown transistor into a high- impedance state, write to the i/o control registers (f2h and f3h). to read the voltage levels present on the i/o pins, read the i/o status registers (f8h and f9h). to determine the status of the output register, read the i/o control registers and the pullup resistor registers. the i/o control registers and the pullup enable registers are all sram shadowed eeprom registers. it is possible to disable the eeprom writes of the regis- ters using the see bit in the configuration register. this reduces the time required to write to the register and increases the amount of times the i/o pins can be adjusted before the eeprom is worn out. memory map and memory types the ds4520 memory map is shown in table 1. three different types of memory are present in the ds4520: eeprom, sram shadowed eeprom, and sram. memory locations specified as eeprom are nv. writing to these locations results in an eeprom write cycle for a time specified by t wr in the ac electrical characteristics table. locations specified as sram shadowed eeprom can be configured to operate in one of two modes specified by the see bit (the lsb of the configuration register, f4h). when the see bit = 0 (default), the memory location acts like eeprom. however, when see = 1, shadow sram is written to instead of the eeprom. this eliminates both the eeprom write time, t rw , as well as the concern of wearing out the eeprom. this is ideal for applications that wish to constantly write to the i/os. power-up default states can be programmed for the i/os in eeprom (with see = 0) and then once powered-up, see can be written to a 1 so the i/os can be updated periodically in sram. the final type of memory present in the ds4520 is standard sram. slave address and address pins the ds4520? slave address is determined by the state of the a0, a1, and a2 address pins as shown in figure 1. address pins connected to gnd result in a ??in the cor- responding bit position in the slave address. conversely, address pins connected to v cc result in a ??in the cor- responding bit positions. i 2 c communication is described in detail in a later section. i 2 c serial interface description i 2 c definitions the following terminology is commonly used to describe i 2 c data transfers. master device: the master device controls the slave devices on the bus. the master device generates scl clock pulses, start, and stop conditions. slave devices: slave devices send and receive data at the master? request. bus idle or not busy: time between stop and start conditions when both sda and scl are inactive and in their logic-high states. when the bus is idle it often initi- ates a low-power mode for slave devices. start condition: a start condition is generated by the master to initiate a new data transfer with a slave. transitioning sda from high to low while scl remains high generates a start condition. see the timing dia- gram for applicable timing. stop condition: a stop condition is generated by the master to end a data transfer with a slave. transitioning sda from low to high while scl remains high gener- ates a stop condition. see the timing diagram for applicable timing. repeated start condition: the master can use a repeated start condition at the end of one data transfer to indicate that it immediately initiates a new data trans- fer following the current one. repeated starts are com- monly used during read operations to identify a specific memory address to begin a data transfer. a repeated start condition is issued identically to a normal start condition. see the timing diagram for applicable timing. bit write: transitions of sda must occur during the low state of scl. the data on sda must remain valid and unchanged during the entire high pulse of scl plus the setup and hold time requirements (see figure 2). data is shifted into the device during the rising edge of the scl.
ds4520 9-bit i 2 c nonvolatile i/o expander plus memory _____________________________________________________________________ 7 *the slave address is determined by address pins a0, a1, and a2. 1 msb slave address* read/write bit lsb 010 a2 a1 a0 r/w figure 1. ds4520 slave address byte table 1. ds4520 memory map address type name function factory default 00h to 3fh eeprom user memory 64 bytes of general-purpose user eeprom. 00h 40 to e7h reserved undefined address space for future expansion. reads and writes to this space have no effect on the device. e8 to efh eeprom reserved f0h pullup enable 0 pullup enable for i/o_0 to i/o_7. i/o_0 is the lsb and i/o_7 is the msb. set the corresponding bit to enable the pullup; clear the bit to disable the pullup. 00h f1h pullup enable 1 pullup enable for i/o_8. i/o_8 is the lsb. only the lsb is used. set the lsb bit to enable the pullup on i/o_8; clear the lsb to disable the pullup. 00h f2h i/o control 0 i/o control for i/o_0 to i/o_7. i/o_0 is the lsb and i/o_7 is the msb. clearing the corresponding bit of the register pulls the selected i/o pin low; setting the bit places the pulldown transistor into a high-impedance state. when the pulldown is high impedance, the output floats if no pullup/down is connected to the pin. ffh f3h i/o control 1 i/o control for i/o_8. i/o_8 is the lsb. only the lsb is used. clearing the lsb of the register pulls the i/o_8 pin low; setting the lsb places the pulldown transistor into a high-impedance state. when the pulldown is high impedance, the output floats if no pullup/down is connected to the pin. 01h f4h configuration configuration register. the lsb is the see bit. when set, this bit disables writes to the eeprom; writing only affects the shadow sram. when set to 0, both the eeprom and the shadow sram is written. 00h f5h to f7h sram shadowed eeprom [eeprom writes are disabled if the see bit = 1] user memory 3 bytes of general-purpose user eeprom. 00h f8h i/o status 0 i/o status for i/o_0 to i/o_7. i/o_0 is the lsb and i/o_7 is the msb. writing to this register has no effect. read this register to determine the state of the i/o_0 to i/o_7 pins. f9h i/o status 1 i/o status for i/o_8. i/o_8 is the lsb. only the lsb is used; the other bits could be any value when read. writing to this register has no effect. read this register to determine the state of the i/o_8 pin. fah to ffh sram sram user 6 bytes of general-purpose sram.
ds4520 9-bit i 2 c nonvolatile i/o expander plus memory 8 _____________________________________________________________________ bit read: at the end a write operation, the master must release the sda bus line for the proper amount of setup time before the next rising edge of scl during a bit read (see figure 2). the device shifts out each bit of data on sda at the falling edge of the previous scl pulse and the data bit is valid at the rising edge of the current scl pulse. remember that the master gener- ates all scl clock pulses including when it is reading bits from the slave. acknowledgement (ack and nack): an acknowledge- ment (ack) or not acknowledge (nack) is always the 9th bit transmitted during a byte transfer. the device receiving data (the master during a read or the slave during a write operation) performs an ack by transmitting a zero during the 9th bit. a device performs a nack by transmitting a one during the 9th bit. timing (figure 2) for the ack and nack is identical to all other bit writes. an ack is the acknowledgement that the device is properly receiving data. a nack is used to terminate a read sequence or as an indication that the device is not receiving data. byte write: a byte write consists of 8 bits of informa- tion transferred from the master to the slave (most sig- nificant bit first) plus a 1-bit acknowledgement from the slave to the master. the 8 bits transmitted by the mas- ter are done according to the bit write definition and the acknowledgement is read using the bit read definition. byte read: a byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ack or nack from the master to the slave. the 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit read definition above, and the master transmits an ack using the bit write definition to receive additional data bytes. the master must nack the last byte read to ter- minated communication so the slave returns control of sda to the master. slave address byte: each slave on the i 2 c bus responds to a slave address byte sent immediately fol- lowing a start condition. the slave address byte con- tains the slave address in the most significant 7 bits and the r/ w bit in the least significant bit. the ds4520? slave address is determined by the state of the a0, a1, and a2 address pins as shown in figure 1. address pins connected to gnd result in a ??in the corresponding bit position in the slave address. conversely, address pins connected to v cc result in a ??in the corresponding bit positions. when the r/ w bit is 0 (such as in a0h), the master is indicating it will write data to the slave. if r/ w = 1, (a1h in this case), the master is indicating it will read from the slave. sda scl t hd:sta t low t high t r t f t buf t hd:dat t su:dat repeated start t su:sta t hd:sta t su:sto t sp stop start note: timing is referenced to v il(max) and v ih(min) figure 2. i 2 c timing diagram
if an incorrect slave address is written, the ds4520 assumes the master is communicating with another i 2 c device and ignores the communication until the next start condition is sent. memory address: during an i 2 c write operation, the master must transmit a memory address to identify the memory location where the slave is to store the data. the memory address is always the second byte trans- mitted during a write operation following the slave address byte. i 2 c communication writing a single byte to a slave: the master must generate a start condition, write the slave address byte (r/ w = 0), write the memory address, write the byte of data, and generate a stop condition. remember the master must read the slave? acknowledgement during all byte write operations. writing multiple bytes to a slave: to write multiple bytes to a slave, the master generates a start condition, writes the slave address byte (r/ w = 0), writes the memory address, writes up to 8 data bytes, and gener- ates a stop condition. the ds4520 is capable of writing up to 8 bytes (one page or row) with a single write transaction. this is internally controlled by an address counter that allows data to be written to consecutive addresses without transmitting a memory address before each data byte is sent. the address counter limits the write to one 8- byte page. attempts to write to additional pages of memory without sending a stop condition between pages results in the address counter wrapping around to the beginning of the present row. the first row begins at address 00h and subsequent rows begin at multiples of 8 there on (08h, 10h, 18h, 20h, etc). to prevent address wrapping from occurring, the mas- ter must send a stop condition at the end of the page, and then wait for the bus free or eeprom write time to elapse. then the master can generate a new start con- dition, write the slave address byte (r/ w = 0), and the first memory address of the next memory row before continuing to write data. acknowledge polling: any time an eeprom page is written, the ds4520 requires the eeprom write time (t w ) after the stop condition to write the contents of the page to eeprom. during the eeprom write time, the device does not acknowledge its slave address because it is busy. it is possible to take advantage of this phenomenon by repeatedly addressing the ds4520, which allows communication to continue as soon as the device is ready. the alternative to acknowl- edge polling is to wait for a maximum period of t w to elapse before attempting to access the device. eeprom write cycles: when eeprom writes occur, the ds4520 writes the whole eeprom memory page even if only a single byte on a page was modified. writes that do not modify all 8 bytes on the page are valid and do not corrupt any other bytes on the same page. because the whole page is written, even bytes on the page that were not modified during the transac- tion are still subject to a write cycle. the ds4520? eeprom write cycles are specified in the nonvolatile memory characteristics table. the specification shown is at the worst-case temperature. it is capable of han- dling approximately 10x that many writes at room tem- perature. reading a single byte from a slave: unlike the write operation that uses the specified memory address byte to define where the data is to be written, the read oper- ation occurs at the present value of the memory address counter. to read a single byte from the slave, the master generates a start condition, writes the slave address byte with r/ w = 1, reads the data byte with a nack to indicate the end of the transfer, and generates a stop condition. however, since requiring the master to keep track of the memory address counter is imprac- tical, the following method should be used to perform reads from a specified memory location. manipulating the address counter for reads: a dummy write cycle can be used to force the address counter to a particular value. to do this the master gen- erates a start condition, writes the slave address byte (r/ w = 0), writes the memory address where it desires to read, generates a repeated start condition, writes the slave address byte (r/ w = 1), reads data with ack or nack as applicable, and generates a stop condition. ds4520 9-bit i 2 c nonvolatile i/o expander plus memory _____________________________________________________________________ 9
ds4520 9-bit i 2 c nonvolatile i/o expander plus memory maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 10 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2004 maxim integrated products printed usa is a registered trademark of maxim integrated products. is a registered trademark of dallas semiconductor corporation. slave address* start start 1 0 1 0 a2 a1 a0 r/w slave ack slave ack slave ack msb lsb msb lsb msb lsb b7 b6 b5 b4 b3 b2 b1 b0 read/ write register address b7 b6 b5 b4 b3 b2 b1 b0 data stop single byte write -write i/o control 0 register to 00h single byte write -write pullup enable 0 register to ffh single byte read -read i/o status 0 resister two byte write -write i/o control 0 and i/o control 1 registers to 00h start stop 1 0100000 11110 010 a0h f2h start repeated start a1h master nack stop 1 0100000 11111 000 f8h 10100 001 1 0100000 11110 010 a0h f2h stop i/o status start 1 0100000 11110 000 a0h f0h stop d ata ffh 00h 00h example i 2 c transactions (when a0, a1, and a2 are connected to gnd) typical i 2 c write transaction *the slave address is determined by address pins a0, a1, and a2. 00000 000 1 1 111 111 a0h 00000000 two byte read -read i/o status 0 and i/o status 1 rgisters a) c) b) d) d) start stop 101000 00 111 11000 a0h f8h a1h 1010 0001 i/o status 0 data i/o status 1 data slave ack slave ack slave ack slave ack slave ack slave ack slave ack slave ack slave ack slave ack slave ack slave ack slave ack slave ack slave ack slave ack master ack master nack repeated start 00000000 figure 3. i 2 c communication examples see figure 3 for a read example using the repeated start condition to specify the starting memory location. reading multiple bytes from a slave: the read oper- ation can be used to read multiple bytes with a single transfer. when reading bytes from the slave, the master simply acks the data byte if it desires to read another byte before terminating the transaction. after the mas- ter reads the last byte it must nack to indicate the end of the transfer and generates a stop condition. applications information power-supply decoupling to achieve best results, it is highly recommended that a decoupling capacitor is used on the ic power-supply pins. typical values of decoupling capacitors are 0.01? and 0.1?. use a high-quality, ceramic, surface-mount capacitor, and mount it as close as possible to the v cc and gnd pins of the ic to minimize lead inductance. chip topology transistor count: 14,398 substrate connected to ground pac ka ge information for the latest package outline information, go to www.maxim-ic.com/dallaspackinfo .
e nglish ? ???? ? ??? ? ??? what's ne w p roducts solutions de sign ap p note s sup p ort buy comp any me mbe rs ds4520 part number table notes: see the ds4520 quickview data sheet for further information on this product family or download the ds4520 full data sheet (pdf, 984kb). 1. other options and links for purchasing parts are listed at: http://www.maxim-ic.com/sales . 2. didn't find what you need? ask our applications engineers. expert assistance in finding parts, usually within one business day. 3. part number suffixes: t or t&r = tape and reel; + = rohs/lead-free; # = rohs/lead-exempt. more: see full data sheet or part naming c onventions . 4. * some packages have variations, listed on the drawing. "pkgc ode/variation" tells which variation the product uses. 5. part number free sample buy direct package: type pins size drawing code/var * temp rohs/lead-free? materials analysis ds4520e+ tssop;16 pin;173 dwg: 56-g2019-000a (pdf) use pkgcode/variation: u16+1 * -40c to +85c rohs/lead-free: yes materials analysis ds4520e tssop;16 pin;173 dwg: 56-g2019-000a (pdf) use pkgcode/variation: u16-1 * -40c to +85c rohs/lead-free: no materials analysis ds4520e+trl tssop;16 pin;173 dwg: 56-g2019-000a (pdf) use pkgcode/variation: u16+1 * -40c to +85c rohs/lead-free: yes materials analysis didn't find what you need? c ontac t us: send us an email c opyright 2 0 0 7 by m axim i ntegrated p roduc ts , dallas semic onduc tor ? legal n otic es ? p rivac y p olic y

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